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    <title>OpenDaylight JIRA</title>
    <link>https://jira.opendaylight.org</link>
    <description>This file is an XML representation of an issue</description>
    <language>en-us</language>    <build-info>
        <version>8.20.10</version>
        <build-number>820010</build-number>
        <build-date>22-06-2022</build-date>
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<item>
            <title>[TRNSPRTPCE-348] Portmapping fails when xponder subtree is not fully populated</title>
                <link>https://jira.opendaylight.org/browse/TRNSPRTPCE-348</link>
                <project id="10178" key="TRNSPRTPCE">transportpce</project>
                    <description>&lt;p&gt;We noticed that there are cases where, xponder subtree may not have all the connection map details. Below is an example:&lt;/p&gt;

&lt;p&gt;&#160;&lt;/p&gt;

&lt;p&gt;&#160;&lt;/p&gt;
&lt;div class=&quot;preformatted panel&quot; style=&quot;border-width: 1px;&quot;&gt;&lt;div class=&quot;preformattedContent panelContent&quot;&gt;
&lt;pre&gt;&amp;lt;xponder&amp;gt;
	&amp;lt;xpdr-number&amp;gt;2&amp;lt;/xpdr-number&amp;gt;
	&amp;lt;xpdr-port&amp;gt;
		&amp;lt;index&amp;gt;2&amp;lt;/index&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
		&amp;lt;eqpt-srg-id&amp;gt;1&amp;lt;/eqpt-srg-id&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-1-4&amp;lt;/circuit-pack-name&amp;gt;
	&amp;lt;/xpdr-port&amp;gt;
	&amp;lt;xpdr-port&amp;gt;
		&amp;lt;index&amp;gt;1&amp;lt;/index&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
		&amp;lt;eqpt-srg-id&amp;gt;1&amp;lt;/eqpt-srg-id&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-1-3&amp;lt;/circuit-pack-name&amp;gt;
	&amp;lt;/xpdr-port&amp;gt;
	&amp;lt;xpdr-type&amp;gt;tpdr&amp;lt;/xpdr-type&amp;gt;
&amp;lt;/xponder&amp;gt;
&amp;lt;xponder&amp;gt;
	&amp;lt;xpdr-number&amp;gt;1&amp;lt;/xpdr-number&amp;gt;
	&amp;lt;xpdr-port&amp;gt;
		&amp;lt;index&amp;gt;2&amp;lt;/index&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
		&amp;lt;eqpt-srg-id&amp;gt;1&amp;lt;/eqpt-srg-id&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-1-2&amp;lt;/circuit-pack-name&amp;gt;
	&amp;lt;/xpdr-port&amp;gt;
	&amp;lt;xpdr-port&amp;gt;
		&amp;lt;index&amp;gt;1&amp;lt;/index&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
		&amp;lt;eqpt-srg-id&amp;gt;1&amp;lt;/eqpt-srg-id&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-1-1&amp;lt;/circuit-pack-name&amp;gt;
	&amp;lt;/xpdr-port&amp;gt;
	&amp;lt;recolor&amp;gt;false&amp;lt;/recolor&amp;gt;
	&amp;lt;xpdr-type&amp;gt;tpdr&amp;lt;/xpdr-type&amp;gt;
&amp;lt;/xponder&amp;gt;
&amp;lt;connection-map&amp;gt;
	&amp;lt;connection-map-number&amp;gt;16843777&amp;lt;/connection-map-number&amp;gt;
	&amp;lt;destination&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-1-3&amp;lt;/circuit-pack-name&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
	&amp;lt;/destination&amp;gt;
	&amp;lt;source&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-1-4&amp;lt;/circuit-pack-name&amp;gt;
	&amp;lt;/source&amp;gt;
&amp;lt;/connection-map&amp;gt;
&amp;lt;connection-map&amp;gt;
	&amp;lt;connection-map-number&amp;gt;16843521&amp;lt;/connection-map-number&amp;gt;
	&amp;lt;destination&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-1-4&amp;lt;/circuit-pack-name&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
	&amp;lt;/destination&amp;gt;
	&amp;lt;source&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-1-3&amp;lt;/circuit-pack-name&amp;gt;
	&amp;lt;/source&amp;gt;
&amp;lt;/connection-map&amp;gt;
&amp;lt;connection-map&amp;gt;
	&amp;lt;connection-map-number&amp;gt;16843265&amp;lt;/connection-map-number&amp;gt;
	&amp;lt;destination&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-1-1&amp;lt;/circuit-pack-name&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
	&amp;lt;/destination&amp;gt;
	&amp;lt;source&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-1-2&amp;lt;/circuit-pack-name&amp;gt;
	&amp;lt;/source&amp;gt;
&amp;lt;/connection-map&amp;gt;
&amp;lt;connection-map&amp;gt;
	&amp;lt;connection-map-number&amp;gt;16843009&amp;lt;/connection-map-number&amp;gt;
	&amp;lt;destination&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-1-2&amp;lt;/circuit-pack-name&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
	&amp;lt;/destination&amp;gt;
	&amp;lt;source&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-1-1&amp;lt;/circuit-pack-name&amp;gt;
	&amp;lt;/source&amp;gt;
&amp;lt;/connection-map&amp;gt;
&amp;lt;connection-map&amp;gt;
	&amp;lt;connection-map-number&amp;gt;16909313&amp;lt;/connection-map-number&amp;gt;
	&amp;lt;destination&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-2-3&amp;lt;/circuit-pack-name&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
	&amp;lt;/destination&amp;gt;
	&amp;lt;source&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-2-4&amp;lt;/circuit-pack-name&amp;gt;
	&amp;lt;/source&amp;gt;
&amp;lt;/connection-map&amp;gt;
&amp;lt;connection-map&amp;gt;
	&amp;lt;connection-map-number&amp;gt;16909057&amp;lt;/connection-map-number&amp;gt;
	&amp;lt;destination&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-2-4&amp;lt;/circuit-pack-name&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
	&amp;lt;/destination&amp;gt;
	&amp;lt;source&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-2-3&amp;lt;/circuit-pack-name&amp;gt;
	&amp;lt;/source&amp;gt;
&amp;lt;/connection-map&amp;gt;
&amp;lt;connection-map&amp;gt;
	&amp;lt;connection-map-number&amp;gt;16908801&amp;lt;/connection-map-number&amp;gt;
	&amp;lt;destination&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-2-1&amp;lt;/circuit-pack-name&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
	&amp;lt;/destination&amp;gt;
	&amp;lt;source&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-2-2&amp;lt;/circuit-pack-name&amp;gt;
	&amp;lt;/source&amp;gt;
&amp;lt;/connection-map&amp;gt;
&amp;lt;connection-map&amp;gt;
	&amp;lt;connection-map-number&amp;gt;16908545&amp;lt;/connection-map-number&amp;gt;
	&amp;lt;destination&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-2-2&amp;lt;/circuit-pack-name&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
	&amp;lt;/destination&amp;gt;
	&amp;lt;source&amp;gt;
		&amp;lt;port-name&amp;gt;1&amp;lt;/port-name&amp;gt;
		&amp;lt;circuit-pack-name&amp;gt;1-2-1&amp;lt;/circuit-pack-name&amp;gt;
	&amp;lt;/source&amp;gt;
&amp;lt;/connection-map&amp;gt;

&lt;/pre&gt;
&lt;/div&gt;&lt;/div&gt;

&lt;p&gt;In the this case the circuit-packs 1-2-1, 1-2-2, 1-2-3, 1-2-4 does not have xponder substree. While we can manually create xponder subtree in the device for these missing circuit-packs. It would be better if the code throws error for such scenarios, while continue to build the port-mapping.&lt;/p&gt;</description>
                <environment></environment>
        <key id="33556">TRNSPRTPCE-348</key>
            <summary>Portmapping fails when xponder subtree is not fully populated</summary>
                <type id="10104" iconUrl="https://jira.opendaylight.org/secure/viewavatar?size=xsmall&amp;avatarId=10303&amp;avatarType=issuetype">Bug</type>
                                            <priority id="3" iconUrl="https://jira.opendaylight.org/images/icons/priorities/major.svg">Medium</priority>
                        <status id="10004" iconUrl="https://jira.opendaylight.org/images/icons/status_generic.gif" description="">Verified</status>
                    <statusCategory id="3" key="done" colorName="green"/>
                                    <resolution id="10000">Done</resolution>
                                        <assignee username="b95quare">Balagangadhar Bathula</assignee>
                                    <reporter username="b95quare">Balagangadhar Bathula</reporter>
                        <labels>
                    </labels>
                <created>Wed, 11 Nov 2020 20:00:52 +0000</created>
                <updated>Fri, 18 Jun 2021 13:34:10 +0000</updated>
                            <resolved>Wed, 28 Apr 2021 15:19:32 +0000</resolved>
                                                    <fixVersion>Aluminium</fixVersion>
                    <fixVersion>Silicon</fixVersion>
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